3aa071944d
FossilOrigin-Name: c28a8bedba4be3c9865b07b8b67cf4305ee6a244f9e1abb1fc7d2346b308576a
105 lines
2.6 KiB
Text
105 lines
2.6 KiB
Text
# Multiple Cores
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Nga has optional support for multiple virtual cores. These
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are not directly comparable to actual CPU cores, but do
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allow for a degree of multitasking.
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Cores share a single address space for RAM, but each gets
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its own data and address stacks, as well as 24 internal
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registers for private data storage. The floating point stack
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is shared across all cores.
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Execution is handled in a round-robin fashion. After an
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instruction bundle is processed, Nga will pass control to the
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next active core. Note that this means that execution will
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stall when an I/O operation is running.
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## Enabling
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To make use of the multicore support, edit the `Makefile` and
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uncomment the lines reading:
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# ENABLED += -DENABLE_MULTICORE
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# DEVICES += interface/multicore.retro
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And rebuild.
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## Scheduling
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Nga switches to the next active core after execution of an
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instruction bundle completes on the current core.
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## Initialization
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To initialize a core, pass the core identifier (0 through 7)
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to `core:init`. This will zero out its internal registers and
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set it to.
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Example:
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#4 core:init
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## Starting a Core
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Initialization does not activate a core. To do this, you need
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to use `core:start`. Pass this the address of the word to
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run and the core number.
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Example:
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:a [ $a c:put ] forever ;
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&a #4 core:start
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## Pausing a Core
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Two words are provided for suspending a core. The first is
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`core:pause`. Pass this the core number to pause.
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Example:
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#4 core:pause
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The second option is intended if you need the currently
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active core to pause. This word is `core:pause-current`.
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Example:
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core:pause-current
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## Resuming a Core
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To reactive a core, use `core:resume`. This takes the core
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number to activate.
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Example:
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#4 core:resume
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## Registers
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Each core has 24 internal memory spaces. You can read these
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with `core:rr` and modify them with `core:wr`. (These are
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used identically to `fetch` and `store`). Registers are
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numbered as 0 through 23.
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A core can not access the registers in another core.
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## Napia
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The implementation here is based on the multicore model used
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in Napia, the virtual machine being written for the Retro
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on smaller targets. Code written to work with this will be
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usable on Retro/Napia with minimal changes.
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The main differences are that under Nga, this is an optional
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extension, but in Napia, it is part of the standard system.
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## Other Notes
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On startup, execution occurs on core 0, with only core 0 being
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initialized.
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I/O is run on the currently active core. Since I/O is blocking,
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waiting for an interaction to occur will prevent other cores
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from running until the operation is complete.
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