From e2839d5340389f7bcfde1f9c9e5b5d15df49b925 Mon Sep 17 00:00:00 2001
From: crc <crc@noemail.net>
Date: Sun, 17 Feb 2019 18:12:07 +0000
Subject: [PATCH] new example: EDA.forth

FossilOrigin-Name: 3b23f9190a9afe8c18b42a76dd32a08101bd986a39ec0d2993b882d135841cbb
---
 RELEASE_NOTES.md  |  1 +
 example/EDA.forth | 47 +++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 48 insertions(+)
 create mode 100644 example/EDA.forth

diff --git a/RELEASE_NOTES.md b/RELEASE_NOTES.md
index bd8b6d3..c71979f 100644
--- a/RELEASE_NOTES.md
+++ b/RELEASE_NOTES.md
@@ -105,6 +105,7 @@ June 2019.
 - add Buffer.forth
 - add CaptureOutput.forth
 - add DisplayNames.forth
+- add EDA.forth
 - add EvaluateString.forth
 - add FloatVar.forth
 - add Forget.forth
diff --git a/example/EDA.forth b/example/EDA.forth
new file mode 100644
index 0000000..7e7158d
--- /dev/null
+++ b/example/EDA.forth
@@ -0,0 +1,47 @@
+# EDA.forth
+
+## Description
+
+Forth EDA, ported to RETRO
+http://www.0xff.in/bin/A_Language_for_Digital_Design.pdf
+
+## Code & Commentary
+
+~~~
+#32768 'STATUS const
+#32767 'TIME const
+~~~
+
+### Digital logic simulator
+
+~~~
+:S. dup STATUS and n:-zero? [ '+ s:put ] if TIME and n:put ;
+:_ (n-n) STATUS xor ;
+:eda:and (nn-n) over  TIME and over  TIME and n:max rot  STATUS and rot  STATUS and and + ;
+:eda:or (nn-n) _ swap _ eda:and _ ;
+~~~
+
+### Technology
+
+~~~
+:2and (nn-n)  eda:and _ #9 + ;
+:3or  (nnn-n) eda:or eda:or #30 + ;
+:2xor (nn-n)  over _ over eda:and [ _ eda:and ] dip eda:or #35 + ;
+~~~
+
+### Logic equations
+
+~~~
+#0    'A const
+#10   'B const
+#10 _ 'C const
+:enb_ (-n) A B 2xor ; (45)
+:xy   (-n) enb_ C 2and A B 3or ; (+84)
+~~~
+
+## Test
+
+```
+enb_ S. nl
+xy S. nl
+```