END -> HALT in Nga instruction naming
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18 changed files with 45 additions and 45 deletions
14
doc/Nga.md
14
doc/Nga.md
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@ -29,7 +29,7 @@ executed.
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Instruction processing: the **IP** is incremented and the opcode at the
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current address is invoked. This process then repeats. Execution ends
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if the **END** instruction is run or end of memory is reached.
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if the **HALT** instruction is run or end of memory is reached.
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Endian: the image files are stored in little endian format.
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@ -104,7 +104,7 @@ corresponding values (in decimal):
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2 dup 9 ccall 16 store 23 xor
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3 drop 10 return 17 add 24 shift
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4 swap 11 eq 18 sub 25 zret
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5 push 12 neq 19 mul 26 end
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5 push 12 neq 19 mul 26 halt
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6 pop 13 lt 20 divmod 27 io enumerate
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~~~
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@ -112,7 +112,7 @@ enum vm_opcode {
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VM_NOP, VM_LIT, VM_DUP, VM_DROP, VM_SWAP, VM_PUSH, VM_POP,
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VM_JUMP, VM_CALL, VM_CCALL, VM_RETURN, VM_EQ, VM_NEQ, VM_LT,
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VM_GT, VM_FETCH, VM_STORE, VM_ADD, VM_SUB, VM_MUL, VM_DIVMOD,
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VM_AND, VM_OR, VM_XOR, VM_SHIFT, VM_ZRET, VM_END, VM_IO_ENUM,
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VM_AND, VM_OR, VM_XOR, VM_SHIFT, VM_ZRET, VM_HALT, VM_IO_ENUM,
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VM_IO_QUERY, VM_IO_INTERACT
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};
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#define NUM_OPS VM_IO_INTERACT + 1
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@ -333,7 +333,7 @@ Example:
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ccall
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li f
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call
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end
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halt
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~~~
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void inst_ccall() {
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@ -622,10 +622,10 @@ void inst_zret() {
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}
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~~~
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**END** tells Nga that execution should end.
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**HALT** tells Nga that execution should end.
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~~~
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void inst_end() {
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void inst_halt() {
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ip = IMAGE_SIZE;
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}
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~~~
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@ -677,7 +677,7 @@ Handler instructions[NUM_OPS] = {
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inst_nop, inst_lit, inst_dup, inst_drop, inst_swap, inst_push, inst_pop,
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inst_jump, inst_call, inst_ccall, inst_return, inst_eq, inst_neq, inst_lt,
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inst_gt, inst_fetch, inst_store, inst_add, inst_sub, inst_mul, inst_divmod,
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inst_and, inst_or, inst_xor, inst_shift, inst_zret, inst_end, inst_ie,
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inst_and, inst_or, inst_xor, inst_shift, inst_zret, inst_halt, inst_ie,
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inst_iq, inst_ii
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};
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~~~
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@ -47,7 +47,7 @@ gets a two character identifier.
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From the list of instructions:
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0 nop 5 push 10 ret 15 fetch 20 div 25 zret
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1 lit 6 pop 11 eq 16 store 21 and 26 end
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1 lit 6 pop 11 eq 16 store 21 and 26 halt
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2 dup 7 jump 12 neq 17 add 22 or 27 ienum
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3 drop 8 call 13 lt 18 sub 23 xor 28 iquery
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4 swap 9 ccall 14 gt 19 mul 24 shift 29 iinvoke
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@ -55,7 +55,7 @@ From the list of instructions:
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This reduces to:
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0 .. 5 pu 10 re 15 fe 20 di 25 zr
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1 li 6 po 11 eq 16 st 21 an 26 en
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1 li 6 po 11 eq 16 st 21 an 26 ha
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2 du 7 ju 12 ne 17 ad 22 or 27 ie
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3 dr 8 ca 13 lt 18 su 23 xo 28 iq
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4 sw 9 cc 14 gt 19 mu 24 sh 29 ii
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@ -25,7 +25,7 @@ instruction name. For a non operation, use '..' instead of
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'no'.
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0 nop 5 push 10 ret 15 fetch 20 div 25 zret
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1 lit 6 pop 11 eq 16 store 21 and 26 end
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1 lit 6 pop 11 eq 16 store 21 and 26 halt
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2 dup 7 jump 12 neq 17 add 22 or 27 ienum
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3 drop 8 call 13 lt 18 sub 23 xor 28 iquery
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4 swap 9 ccall 14 gt 19 mul 24 shift 29 iinvoke
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@ -44,7 +44,7 @@ An example of a small program:
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i lilica..
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d 12
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r square
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i en......
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i ha......
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As mentioned earlier this requires knowledge of Nga architecture.
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While you can pack up to four instructions per location, you
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@ -27,7 +27,7 @@ architecture. There are 30 instructions, with up to four packed
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into each memory location (*cell*). The instructions are:
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0 nop 5 push 10 ret 15 fetch 20 div 25 zret
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1 lit 6 pop 11 eq 16 store 21 and 26 end
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1 lit 6 pop 11 eq 16 store 21 and 26 halt
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2 dup 7 jump 12 neq 17 add 22 or 27 ienum
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3 drop 8 call 13 lt 18 sub 23 xor 28 iquery
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4 swap 9 ccall 14 gt 19 mul 24 shift 29 iinvoke
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@ -1257,7 +1257,7 @@ for references to named functions.
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~~~
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: Instructions
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d 2116
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d 2116
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d 11340
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d 11700
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d 11400
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@ -1283,7 +1283,7 @@ d 12654
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d 13320
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d 11960
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d 13908
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d 11110
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d 10088
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d 10605
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d 11865
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d 11025
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BIN
ngaImage
BIN
ngaImage
Binary file not shown.
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@ -73,7 +73,7 @@ void read_line(FILE *file, char *line_buffer) {
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}
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CELL opcode_for(char *s) {
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char* opcodeList = "..lidudrswpupojucaccreeqneltgtfestadsumudianorxoshzrenieiqii";
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char* opcodeList = "..lidudrswpupojucaccreeqneltgtfestadsumudianorxoshzrhaieiqii";
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int16_t* s16 = (int16_t *)s;
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int16_t* op16 = (int16_t *)opcodeList;
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int i = 0;
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@ -284,7 +284,7 @@ enum vm_opcode {
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VM_NOP, VM_LIT, VM_DUP, VM_DROP, VM_SWAP, VM_PUSH, VM_POP,
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VM_JUMP, VM_CALL, VM_CCALL, VM_RETURN, VM_EQ, VM_NEQ, VM_LT,
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VM_GT, VM_FETCH, VM_STORE, VM_ADD, VM_SUB, VM_MUL, VM_DIVMOD,
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VM_AND, VM_OR, VM_XOR, VM_SHIFT, VM_ZRET, VM_END, VM_IE,
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VM_AND, VM_OR, VM_XOR, VM_SHIFT, VM_ZRET, VM_HALT, VM_IE,
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VM_IQ, VM_II
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};
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#define NUM_OPS VM_II + 1
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@ -476,7 +476,7 @@ void inst_zret() {
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}
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}
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void inst_end() {
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void inst_halt() {
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ip = IMAGE_SIZE;
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}
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@ -501,7 +501,7 @@ Handler instructions[NUM_OPS] = {
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inst_nop, inst_lit, inst_dup, inst_drop, inst_swap, inst_push, inst_pop,
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inst_jump, inst_call, inst_ccall, inst_return, inst_eq, inst_neq, inst_lt,
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inst_gt, inst_fetch, inst_store, inst_add, inst_sub, inst_mul, inst_divmod,
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inst_and, inst_or, inst_xor, inst_shift, inst_zret, inst_end, inst_ie,
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inst_and, inst_or, inst_xor, inst_shift, inst_zret, inst_halt, inst_ie,
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inst_iq, inst_ii
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};
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@ -408,7 +408,7 @@ enum vm_opcode {
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VM_NOP, VM_LIT, VM_DUP, VM_DROP, VM_SWAP, VM_PUSH, VM_POP,
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VM_JUMP, VM_CALL, VM_CCALL, VM_RETURN, VM_EQ, VM_NEQ, VM_LT,
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VM_GT, VM_FETCH, VM_STORE, VM_ADD, VM_SUB, VM_MUL, VM_DIVMOD,
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VM_AND, VM_OR, VM_XOR, VM_SHIFT, VM_ZRET, VM_END, VM_IE,
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VM_AND, VM_OR, VM_XOR, VM_SHIFT, VM_ZRET, VM_HALT, VM_IE,
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VM_IQ, VM_II
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};
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#define NUM_OPS VM_II + 1
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@ -600,7 +600,7 @@ void inst_zret() {
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}
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}
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void inst_end() {
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void inst_halt() {
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ip = IMAGE_SIZE;
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}
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@ -625,7 +625,7 @@ Handler instructions[NUM_OPS] = {
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inst_nop, inst_lit, inst_dup, inst_drop, inst_swap, inst_push, inst_pop,
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inst_jump, inst_call, inst_ccall, inst_return, inst_eq, inst_neq, inst_lt,
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inst_gt, inst_fetch, inst_store, inst_add, inst_sub, inst_mul, inst_divmod,
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inst_and, inst_or, inst_xor, inst_shift, inst_zret, inst_end, inst_ie,
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inst_and, inst_or, inst_xor, inst_shift, inst_zret, inst_halt, inst_ie,
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inst_iq, inst_ii
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};
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@ -121,7 +121,7 @@ enum vm_opcode {
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VM_NOP, VM_LIT, VM_DUP, VM_DROP, VM_SWAP, VM_PUSH, VM_POP,
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VM_JUMP, VM_CALL, VM_CCALL, VM_RETURN, VM_EQ, VM_NEQ, VM_LT,
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VM_GT, VM_FETCH, VM_STORE, VM_ADD, VM_SUB, VM_MUL, VM_DIVMOD,
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VM_AND, VM_OR, VM_XOR, VM_SHIFT, VM_ZRET, VM_END, VM_IE,
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VM_AND, VM_OR, VM_XOR, VM_SHIFT, VM_ZRET, VM_HALT, VM_IE,
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VM_IQ, VM_II
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};
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#define NUM_OPS VM_II + 1
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@ -330,7 +330,7 @@ void inst_zret() {
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}
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}
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void inst_end() {
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void inst_halt() {
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ip = IMAGE_SIZE;
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}
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@ -355,7 +355,7 @@ Handler instructions[NUM_OPS] = {
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inst_nop, inst_lit, inst_dup, inst_drop, inst_swap, inst_push, inst_pop,
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inst_jump, inst_call, inst_ccall, inst_return, inst_eq, inst_neq, inst_lt,
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inst_gt, inst_fetch, inst_store, inst_add, inst_sub, inst_mul, inst_divmod,
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inst_and, inst_or, inst_xor, inst_shift, inst_zret, inst_end, inst_ie,
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inst_and, inst_or, inst_xor, inst_shift, inst_zret, inst_halt, inst_ie,
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inst_iq, inst_ii
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};
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@ -417,7 +417,7 @@ enum vm_opcode {
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VM_NOP, VM_LIT, VM_DUP, VM_DROP, VM_SWAP, VM_PUSH, VM_POP,
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VM_JUMP, VM_CALL, VM_CCALL, VM_RETURN, VM_EQ, VM_NEQ, VM_LT,
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VM_GT, VM_FETCH, VM_STORE, VM_ADD, VM_SUB, VM_MUL, VM_DIVMOD,
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VM_AND, VM_OR, VM_XOR, VM_SHIFT, VM_ZRET, VM_END, VM_IE,
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VM_AND, VM_OR, VM_XOR, VM_SHIFT, VM_ZRET, VM_HALT, VM_IE,
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VM_IQ, VM_II
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};
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#define NUM_OPS VM_II + 1
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}
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}
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void inst_end() {
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void inst_halt() {
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ip = IMAGE_SIZE;
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}
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@ -659,7 +659,7 @@ Handler instructions[NUM_OPS] = {
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inst_nop, inst_lit, inst_dup, inst_drop, inst_swap, inst_push, inst_pop,
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inst_jump, inst_call, inst_ccall, inst_return, inst_eq, inst_neq, inst_lt,
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inst_gt, inst_fetch, inst_store, inst_add, inst_sub, inst_mul, inst_divmod,
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inst_and, inst_or, inst_xor, inst_shift, inst_zret, inst_end, inst_ie,
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inst_and, inst_or, inst_xor, inst_shift, inst_zret, inst_halt, inst_ie,
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inst_iq, inst_ii
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};
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@ -361,7 +361,7 @@ enum vm_opcode {
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VM_NOP, VM_LIT, VM_DUP, VM_DROP, VM_SWAP, VM_PUSH, VM_POP,
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VM_JUMP, VM_CALL, VM_CCALL, VM_RETURN, VM_EQ, VM_NEQ, VM_LT,
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VM_GT, VM_FETCH, VM_STORE, VM_ADD, VM_SUB, VM_MUL, VM_DIVMOD,
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VM_AND, VM_OR, VM_XOR, VM_SHIFT, VM_ZRET, VM_END, VM_IE,
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VM_AND, VM_OR, VM_XOR, VM_SHIFT, VM_ZRET, VM_HALT, VM_IE,
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VM_IQ, VM_II
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};
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#define NUM_OPS VM_II + 1
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@ -565,7 +565,7 @@ void inst_zret() {
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}
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}
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void inst_end() {
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void inst_halt() {
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ip = IMAGE_SIZE;
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}
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inst_nop, inst_lit, inst_dup, inst_drop, inst_swap, inst_push, inst_pop,
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inst_jump, inst_call, inst_ccall, inst_return, inst_eq, inst_neq, inst_lt,
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inst_gt, inst_fetch, inst_store, inst_add, inst_sub, inst_mul, inst_divmod,
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inst_and, inst_or, inst_xor, inst_shift, inst_zret, inst_end, inst_ie,
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inst_and, inst_or, inst_xor, inst_shift, inst_zret, inst_halt, inst_ie,
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inst_iq, inst_ii
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};
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@ -22,7 +22,7 @@ CELL ngaImage[] = { 1793,14517,15061,15103,202001,0,10,1,10,2,10,3,10,4,10,5,10,
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7,110,2049,105,459009,19,110,459009,54,110,459009,15,110,459009,17,110,1793,5,10,524546,
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158,134284303,160,1807,1025,1642241,227,285282049,343,1,459012,338,117509889,177,338,134287105,343,197,16845825,0,
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351,335,1793,64,17826050,343,247,8,117506305,344,354,64,2116,11340,11700,11400,13685,13104,12432,12402,
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9603,9801,11514,11413,11110,12528,11948,10302,13340,9700,13455,12753,10500,10670,12654,13320,11960,13908,11110,10605,
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9603,9801,11514,11413,11110,12528,11948,10302,13340,9700,13455,12753,10500,10670,12654,13320,11960,13908,10088,10605,
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11865,11025,0,2049,197,987393,1,1793,105,524546,439,2049,437,2049,437,17891588,2,439,8,17045505,
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-24,-16,17043736,-8,1118488,1793,105,17043202,1,169021201,2049,56,25,33883396,101450758,6404,459011,429,34668804,2,
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2049,426,524545,371,429,302056196,371,659969,1,0,9,150,100,117,112,0,448,11,150,100,
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@ -1467,7 +1467,7 @@ enum vm_opcode {
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VM_NOP, VM_LIT, VM_DUP, VM_DROP, VM_SWAP, VM_PUSH, VM_POP,
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VM_JUMP, VM_CALL, VM_CCALL, VM_RETURN, VM_EQ, VM_NEQ, VM_LT,
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VM_GT, VM_FETCH, VM_STORE, VM_ADD, VM_SUB, VM_MUL, VM_DIVMOD,
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VM_AND, VM_OR, VM_XOR, VM_SHIFT, VM_ZRET, VM_END, VM_IE,
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VM_AND, VM_OR, VM_XOR, VM_SHIFT, VM_ZRET, VM_HALT, VM_IE,
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VM_IQ, VM_II
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};
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#define NUM_OPS VM_II + 1
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@ -1677,7 +1677,7 @@ void inst_zret() {
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}
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}
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void inst_end() {
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void inst_halt() {
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ip = IMAGE_SIZE;
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}
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inst_nop, inst_lit, inst_dup, inst_drop, inst_swap, inst_push, inst_pop,
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inst_jump, inst_call, inst_ccall, inst_return, inst_eq, inst_neq, inst_lt,
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inst_gt, inst_fetch, inst_store, inst_add, inst_sub, inst_mul, inst_divmod,
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inst_and, inst_or, inst_xor, inst_shift, inst_zret, inst_end, inst_ie,
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inst_and, inst_or, inst_xor, inst_shift, inst_zret, inst_halt, inst_ie,
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inst_iq, inst_ii
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};
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@ -1748,7 +1748,7 @@ enum vm_opcode {
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VM_NOP, VM_LIT, VM_DUP, VM_DROP, VM_SWAP, VM_PUSH, VM_POP,
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VM_JUMP, VM_CALL, VM_CCALL, VM_RETURN, VM_EQ, VM_NEQ, VM_LT,
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VM_GT, VM_FETCH, VM_STORE, VM_ADD, VM_SUB, VM_MUL, VM_DIVMOD,
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VM_AND, VM_OR, VM_XOR, VM_SHIFT, VM_ZRET, VM_END, VM_IE,
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VM_AND, VM_OR, VM_XOR, VM_SHIFT, VM_ZRET, VM_HALT, VM_IE,
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VM_IQ, VM_II
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};
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#define NUM_OPS VM_II + 1
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@ -1980,7 +1980,7 @@ void inst_zret() {
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}
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}
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void inst_end() {
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void inst_halt() {
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ip = IMAGE_SIZE;
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}
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@ -2005,7 +2005,7 @@ Handler instructions[NUM_OPS] = {
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inst_nop, inst_lit, inst_dup, inst_drop, inst_swap, inst_push, inst_pop,
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inst_jump, inst_call, inst_ccall, inst_return, inst_eq, inst_neq, inst_lt,
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inst_gt, inst_fetch, inst_store, inst_add, inst_sub, inst_mul, inst_divmod,
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inst_and, inst_or, inst_xor, inst_shift, inst_zret, inst_end, inst_ie,
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inst_and, inst_or, inst_xor, inst_shift, inst_zret, inst_halt, inst_ie,
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inst_iq, inst_ii
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};
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@ -31,7 +31,7 @@ namespace Nga
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VM_FETCH, VM_STORE, VM_ADD,
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VM_SUB, VM_MUL, VM_DIVMOD,
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VM_AND, VM_OR, VM_XOR,
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VM_SHIFT, VM_ZRET, VM_END,
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VM_SHIFT, VM_ZRET, VM_HALT,
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VM_IE, VM_IQ, VM_II
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}
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@ -275,7 +275,7 @@ namespace Nga
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ip = address[rsp]; rsp--;
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}
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break;
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case OpCodes.VM_END:
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case OpCodes.VM_HALT:
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ip = 524288 * 16;
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break;
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case OpCodes.VM_IE:
|
||||
|
|
|
@ -80,7 +80,7 @@ function Opcodes() {
|
|||
this.XOR = 23;
|
||||
this.SHIFT = 24;
|
||||
this.ZERO_EXIT = 25;
|
||||
this.END = 26;
|
||||
this.HALT = 26;
|
||||
this.IE = 27;
|
||||
this.IQ = 28;
|
||||
this.II = 29;
|
||||
|
@ -264,7 +264,7 @@ instructions[vm.ZERO_EXIT] = function() {
|
|||
ip = address.pop();
|
||||
}
|
||||
}
|
||||
instructions[vm.END] = function() {
|
||||
instructions[vm.HALT] = function() {
|
||||
ip = IMAGE_SIZE;
|
||||
}
|
||||
instructions[vm.IE] = function() {
|
||||
|
|
|
@ -283,7 +283,7 @@ begin
|
|||
end;
|
||||
end;
|
||||
|
||||
procedure inst_end();
|
||||
procedure inst_halt();
|
||||
begin
|
||||
ip := IMAGE_SIZE - 1;
|
||||
end;
|
||||
|
@ -338,7 +338,7 @@ begin
|
|||
23 : inst_xor();
|
||||
24 : inst_shift();
|
||||
25 : inst_zret();
|
||||
26 : inst_end();
|
||||
26 : inst_halt();
|
||||
27 : inst_in();
|
||||
28 : inst_iq();
|
||||
29 : inst_ii();
|
||||
|
|
|
@ -208,7 +208,7 @@ def i_zr():
|
|||
stack.pop()
|
||||
ip = address.pop()
|
||||
|
||||
def i_en():
|
||||
def i_ha():
|
||||
global ip, memory, stack, address
|
||||
ip = 9000000
|
||||
|
||||
|
@ -224,7 +224,7 @@ def i_ii():
|
|||
stack.pop()
|
||||
rxDisplayCharacter()
|
||||
|
||||
instructions = [i_no, i_li, i_du, i_dr, i_sw, i_pu, i_po, i_ju, i_ca, i_cc, i_re, i_eq, i_ne, i_lt, i_gt, i_fe, i_st, i_ad, i_su, i_mu, i_di, i_an, i_or, i_xo, i_sh, i_zr, i_en, i_ie, i_iq, i_ii]
|
||||
instructions = [i_no, i_li, i_du, i_dr, i_sw, i_pu, i_po, i_ju, i_ca, i_cc, i_re, i_eq, i_ne, i_lt, i_gt, i_fe, i_st, i_ad, i_su, i_mu, i_di, i_an, i_or, i_xo, i_sh, i_zr, i_ha, i_ie, i_iq, i_ii]
|
||||
|
||||
def validateOpcode(opcode):
|
||||
I0 = opcode & 0xFF
|
||||
|
|
Loading…
Reference in a new issue