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nga-c: add NOP skipping

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FossilOrigin-Name: fccadfe87aee74d062c39ad8c6eca33e031afae801c35ed2a2c050b5f6553cec
This commit is contained in:
crc 2023-10-19 16:20:38 +00:00
parent 6ed8f2e962
commit 075fbd6500
3 changed files with 17 additions and 19 deletions
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7
RELEASE-NOTES
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@ -10,8 +10,9 @@
================================================================
- removed duplicate typedef in tools/retro-muri.c (sevan)
- fixed a bug in load_image() in vm/nga-c/retro.c (sevan)
- err:notfound message no longer in vm/nga-c/retro.c (sevan)
- add -v for verbose mode in vm/nga-c/retro.c
- fixed a bug in load_image() (C) (sevan)
- err:notfound message no longer in C (C) (sevan)
- add -v for verbose mode (C)
- now skip execuion of NOP instructions (C)
================================================================

17
tools/retro-extend.c
View file

@ -284,7 +284,7 @@ void execute(CELL cell) {
exit(1);
}
ip++;
if (sp > max_sp) max_sp = sp;
if (sp > max_sp) max_sp = sp;
if (rp > max_rsp) max_rsp = rp;
if (rp == 0)
ip = IMAGE_SIZE;
@ -573,8 +573,7 @@ Handler instructions[] = {
};
void ngaProcessOpcode(CELL opcode) {
if (opcode != 0)
instructions[opcode]();
instructions[opcode]();
}
int ngaValidatePackedOpcodes(CELL opcode) {
@ -591,11 +590,11 @@ int ngaValidatePackedOpcodes(CELL opcode) {
return valid;
}
#define INST(n) ((opcode >> n) & 0xFF) != 0
void ngaProcessPackedOpcodes(CELL opcode) {
CELL raw = opcode;
int i;
for (i = 0; i < 4; i++) {
ngaProcessOpcode(raw & 0xFF);
raw = raw >> 8;
}
if (INST(0)) instructions[opcode & 0xFF]();
if (INST(8)) instructions[(opcode >> 8) & 0xFF]();
if (INST(16)) instructions[(opcode >> 16) & 0xFF]();
if (INST(24)) instructions[(opcode >> 24) & 0xFF]();
}

12
vm/nga-c/retro.c
View file

@ -1596,14 +1596,12 @@ void verbose_details(NgaState *vm, CELL opcode) {
fprintf(stderr, "opcode: %lld\n", opcode);
}
#define INST(n) ((opcode >> n) & 0xFF) != 0
void process_opcode_bundle(NgaState *vm, CELL opcode) {
CELL raw = opcode;
int i;
if (verbose) { verbose_details(vm, opcode); }
for (i = 0; i < 4; i++) {
process_opcode(vm, raw & 0xFF);
raw = raw >> 8;
}
if (INST(0)) instructions[opcode & 0xFF](vm);
if (INST(8)) instructions[(opcode >> 8) & 0xFF](vm);
if (INST(16)) instructions[(opcode >> 16) & 0xFF](vm);
if (INST(24)) instructions[(opcode >> 24) & 0xFF](vm);
}
#ifdef NEEDS_STRL