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fix several invalid instruction bundles

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crc 2024-09-03 16:54:08 +02:00
parent 447e57b7a1
commit ab200ab44f
2 changed files with 5 additions and 5 deletions
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ilo.rom
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konilo.pali
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@ -1488,7 +1488,7 @@ r a:map
i dulieqli i dulieqli
d 95 d 95
r s:rewrite.replace r s:rewrite.replace
i liju.. i liju....
r if r if
: s:rewrite.replace : s:rewrite.replace
@ -1652,7 +1652,7 @@ c (c-s) '_ s:temp tuck #0 s:store ;
i lilica.. i lilica..
r c:to-s.temp r c:to-s.temp
r s:temp r s:temp
i luca.... i lica....
r tuck r tuck
i liliju.. i liliju..
d 0 d 0
@ -3389,7 +3389,7 @@ c (n-a) #64 n:mul block:buffer n:add ;
i limuliad i limuliad
d 64 d 64
r sys:buffers/block r sys:buffers/block
i re.... i re......
: e:line : e:line
c (n-) e:to-line #64 [ fetch-next c:put ] times drop nl ; c (n-) e:to-line #64 [ fetch-next c:put ] times drop nl ;
@ -3442,7 +3442,7 @@ r I
i duliltli i duliltli
d 10 d 10
r sp r sp
i lica.. i lica....
r if r if
i lica.... i lica....
r n:put r n:put
@ -3718,7 +3718,7 @@ r s:get/line.process
: e:erase/line : e:erase/line
c (n-) c (n-)
c e:to-line #32 swap #64 fill ; c e:to-line #32 swap #64 fill ;
i lica... i lica....
r e:to-line r e:to-line
i liswli.. i liswli..
d 32 d 32